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VIMS Registers
7.7.2 FLASH Registers
Table 7-7 lists the memory-mapped registers for the FLASH. All register offset addresses not listed in
Table 7-7 should be considered as reserved locations and the register contents should not be modified.
Table 7-7. FLASH Registers
Offset Acronym Register Name Section
1Ch STAT FMC and Efuse Status Section 7.7.2.1
24h CFG Configuration Section 7.7.2.2
28h SYSCODE_START Syscode Start Address Offset Configuration Section 7.7.2.3
2Ch FLASH_SIZE Flash Size Configuration Section 7.7.2.4
3Ch FWLOCK Firmware Lock Section 7.7.2.5
40h FWFLAG Firmware Flags Section 7.7.2.6
1000h EFUSE E-Fuse instruction register Section 7.7.2.7
1004h EFUSEADDR E-Fuse address register Section 7.7.2.8
1008h DATAUPPER E-Fuse data register - upper Section 7.7.2.9
100Ch DATALOWER E-fuse data register - lower Section 7.7.2.10
1010h EFUSECFG OCP standard system configuration register Section 7.7.2.11
1014h EFUSESTAT System Status Section 7.7.2.12
1018h ACC Arbitrary Instruction count Section 7.7.2.13
101Ch BOUNDARY Boundary test register to drive I/O Section 7.7.2.14
1020h EFUSEFLAG Efuse Key Loaded Flag Section 7.7.2.15
1024h EFUSEKEY Efuse Key Section 7.7.2.16
1028h EFUSERELEASE Efuse Release Section 7.7.2.17
102Ch EFUSEPINS Efuse Pins Section 7.7.2.18
1030h EFUSECRA Efuse Column Repair Address Section 7.7.2.19
1034h EFUSEREAD Efuse Read Section 7.7.2.20
1038h EFUSEPROGRAM Efuse Program Section 7.7.2.21
103Ch EFUSEERROR Efuse Error Section 7.7.2.22
1040h SINGLEBIT Single-Bit Error Status Section 7.7.2.23
1044h TWOBIT Two-Bit Error Status Section 7.7.2.24
1048h SELFTESTCYC Self-Test Cycles Section 7.7.2.25
104Ch SELFTESTSIGN Self-Test Signature Section 7.7.2.26
2000h FRDCTL FMC Read Control Section 7.7.2.27
2004h FSPRD FMC Read Margin Control Section 7.7.2.28
2008h FEDACCTL1 FMC Error Correction Control 1 Section 7.7.2.29
201Ch FEDACSTAT FMC Error Status Section 7.7.2.30
2030h FBPROT FMC Bank Protection Section 7.7.2.31
2034h FBSE FMC Bank Sector Enable Section 7.7.2.32
2038h FBBUSY FMC Bank Busy Section 7.7.2.33
203Ch FBAC FMC Bank Access Control Section 7.7.2.34
2040h FBFALLBACK FMC Bank Fallback Power Section 7.7.2.35
2044h FBPRDY FMC Bank/Pump Ready Section 7.7.2.36
2048h FPAC1 FMC Pump Access Control 1 Section 7.7.2.37
204Ch FPAC2 FMC Pump Access Control 2 Section 7.7.2.38
2050h FMAC FMC Module Access Control Section 7.7.2.39
2054h FMSTAT FMC Module Status Section 7.7.2.40
2064h FLOCK FMC Flash Lock Section 7.7.2.41
2080h FVREADCT FMC VREADCT Trim Section 7.7.2.42
2084h FVHVCT1 FMC VHVCT1 Trim Section 7.7.2.43
2088h FVHVCT2 FMC VHVCT2 Trim Section 7.7.2.44
543
SWCU117A–February 2015–Revised March 2015 Versatile Instruction Memory System (VIMS)
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