User manual

VIMS Configurations www.ti.com
7.1.2 VIMS Flash Line Buffering
The VIMS module contains two flash line buffers because the flash word size is 64 bits.
• A line buffer is placed in the flash CPU bus path that is controlled by the [VIMS.CTL.IDCODE_LB_DIS]
register.
• A line buffer is placed in the flash system bus path that is controlled by the
[VIMS.CTL.SYSBUS_LB_DIS] register.
The objectives of the buffers are to prevent refetching the 32-bit part of the data that has already been
fetched (but not used) in a previous cycle. The status of the line buffers can be found in the
[VIMS.STATUS.IDCODE _LB_DIS] register and thr [VIMS.STATUS.SYSBUS_LB_DIS] register.
7.1.3 VIMS Arbitration
The VIMS provides arbitration between the CPU bus and the system bus. The arbitration is configurable
between round-robin and static, through the [VIMS.CTL.ARB_CFG] register. The static arbitration is
enabled by default and gives the CPU priority over system bus accesses.
The system arbiter allows accesses to occur simultaneously, provided that the CPU bus and the system
bus have different target memories. If, for example, a CPU access causes a cache hit, a system bus
access can access the flash simultaneously.
7.1.4 VIMS Cache TAG Prefetch
The cache contains a TAG prefetch system that automatically prefetches the TAG data for the next 64-bit
address. This feature is controlled through the [VIMS.CTL.PREF_EN] register, and is only enabled if VIMS
mode is set to cache mode. Any access using a prefetched TAG saves one CLK cycle in the access
because tag lookup can be skipped. A prefetch hit is defined as an access using prefetched TAG data and
data that is available in the cache.
TAG prefetch is mainly intended for performance optimization when the CPU is running at full speed. If the
CPU is not running at full speed, there will be no performance optimization, and the TAG prefetch system
must be disabled.
7.2 VIMS Software (SW) Remarks
When the flash is programmed or updated, or when the VIMS domain is entering power down special care
must be taken from the SW side.
The following remarks are automatically taken care of when using in-built ROM functions and the standard
API functions. However, custom code must take the following remarks into account.
7.2.1 Flash Program or Update
Before updating the flash, the VIMS cache and line buffers must be invalidated and flushed to prevent old
data or instructions from being fetched from the cache or line buffers after a flash program or update.
Hence, the VIMS mode must be set to GPRAM or OFF mode before programming, and both VIMS flash
line buffers must be set to disabled.
7.2.2 VIMS Retention
The VIMS domain can be kept in retention, if needed, when the domain is entering power down. The
retention control has the option to specify which memories (internal TAG RAM and cache RAM) will be
kept in retention together with VIMS logic.
NOTE: If the whole MCU domain is powered off, the VIMS domain will not support retention.
Table 7-1 specifies the valid retention combination for VIMS memory:
534
Versatile Instruction Memory System (VIMS) SWCU117A–February 2015–Revised March 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated