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Table 6-100. STAT1 Register Field Descriptions (continued)
Bit Field Type Reset Description
6 SCLK_MF_GOOD R X
SCLK_MF_GOOD
5 SCLK_LF_GOOD R X
SCLK_LF_GOOD
4 ACLK_ADC_GOOD R X
ACLK_ADC_GOOD
3 ACLK_TDC_GOOD R X
ACLK_TDC_GOOD
2 ACLK_REF_GOOD R X
ACLK_REF_GOOD
1 CLK_CHP_GOOD R X
CLK_CHP_GOOD
0 CLK_DCDC_GOOD R X
CLK_DCDC_GOOD
527
SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management
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