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6.2.4.11 XOSCHFCTL Register (Offset = 28h) [reset = X]
XOSCHFCTL is shown in Figure 6-91 and described in Table 6-96.
XOSCHF Control
Figure 6-91. XOSCHFCTL Register
31 30 29 28 27 26 25 24
RESERVED
R/W-X
23 22 21 20 19 18 17 16
RESERVED
R/W-X
15 14 13 12 11 10 9 8
RESERVED PEAK_DET_ITRIM
R/W-X R/W-X
7 6 5 4 3 2 1 0
RESERVED BYPASS RESERVED HP_BUF_ITRIM LP_BUF_ITRIM
R/W-X R/W-X R/W-X R/W-X R/W-X
Table 6-96. XOSCHFCTL Register Field Descriptions
Bit Field Type Reset Description
31-10 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
9-8 PEAK_DET_ITRIM R/W X
Internal. Only to be used through TI provided API.
7 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
6 BYPASS R/W X
Internal. Only to be used through TI provided API.
5 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
4-2 HP_BUF_ITRIM R/W X
Internal. Only to be used through TI provided API.
1-0 LP_BUF_ITRIM R/W X
Internal. Only to be used through TI provided API.
521
SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management
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