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6.2.4.10 ADCDOUBLERNANOAMPCTL Register (Offset = 24h) [reset = X]
ADCDOUBLERNANOAMPCTL is shown in Figure 6-90 and described in Table 6-95.
ADC Doubler Nanoamp Control
Figure 6-90. ADCDOUBLERNANOAMPCTL Register
31 30 29 28 27 26 25 24
RESERVED NANOAMP_BI
AS_ENABLE
R/W-X R/W-X
23 22 21 20 19 18 17 16
SPARE23 RESERVED
R/W-X R/W-X
15 14 13 12 11 10 9 8
RESERVED
R/W-X
7 6 5 4 3 2 1 0
RESERVED ADC_SH_MOD ADC_SH_VBU RESERVED ADC_IREF_CTRL
E_EN F_EN
R/W-X R/W-X R/W-X R/W-X R/W-X
Table 6-95. ADCDOUBLERNANOAMPCTL Register Field Descriptions
Bit Field Type Reset Description
31-25 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
24 NANOAMP_BIAS_ENABL R/W X
Internal. Only to be used through TI provided API.
E
23 SPARE23 R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior
22-6 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
5 ADC_SH_MODE_EN R/W X
Internal. Only to be used through TI provided API.
4 ADC_SH_VBUF_EN R/W X
Internal. Only to be used through TI provided API.
3-2 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
1-0 ADC_IREF_CTRL R/W X
Internal. Only to be used through TI provided API.
520
Power, Reset, and Clock Management SWCU117A–February 2015–Revised March 2015
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