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6.2.4.9 ATESTCTL Register (Offset = 20h) [reset = X]
ATESTCTL is shown in Figure 6-89 and described in Table 6-94.
Analog Test Control
Figure 6-89. ATESTCTL Register
31 30 29 28 27 26 25 24
SPARE30 SCLK_LF_AUX RESERVED
_EN
R/W-X R/W-X R/W-X
23 22 21 20 19 18 17 16
RESERVED
R/W-X
15 14 13 12 11 10 9 8
RESERVED
R/W-X
7 6 5 4 3 2 1 0
RESERVED
R/W-X
Table 6-94. ATESTCTL Register Field Descriptions
Bit Field Type Reset Description
31-30 SPARE30 R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
29 SCLK_LF_AUX_EN R/W X
Enable 32 kHz clock to AUX_COMPB.
28-0 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
519
SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management
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