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6.2.4.3 RADCEXTCFG Register (Offset = 8h) [reset = X]
RADCEXTCFG is shown in Figure 6-83 and described in Table 6-88.
RADC External Configuration
Figure 6-83. RADCEXTCFG Register
31 30 29 28 27 26 25 24
HPM_IBIAS_WAIT_CNT
R/W-X
23 22 21 20 19 18 17 16
HPM_IBIAS_WAIT_CNT LPM_IBIAS_WAIT_CNT
R/W-X R/W-X
15 14 13 12 11 10 9 8
IDAC_STEP RADC_DAC_TH
R/W-X R/W-X
7 6 5 4 3 2 1 0
RADC_DAC_TH RADC_MODE_ RESERVED
IS_SAR
R/W-X R/W-X R/W-X
Table 6-88. RADCEXTCFG Register Field Descriptions
Bit Field Type Reset Description
31-22 HPM_IBIAS_WAIT_CNT R/W X
Internal. Only to be used through TI provided API.
21-16 LPM_IBIAS_WAIT_CNT R/W X
Internal. Only to be used through TI provided API.
15-12 IDAC_STEP R/W X
Internal. Only to be used through TI provided API.
11-6 RADC_DAC_TH R/W X
Internal. Only to be used through TI provided API.
5 RADC_MODE_IS_SAR R/W X
Internal. Only to be used through TI provided API.
4-0 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
513
SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management
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