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6.2.4.2 CTL1 Register (Offset = 4h) [reset = X]
CTL1 is shown in Figure 6-82 and described in Table 6-87.
Control 1 This register contains various OSC_DIG configuration
Figure 6-82. CTL1 Register
31 30 29 28 27 26 25 24
RESERVED
R/W-X
23 22 21 20 19 18 17 16
RESERVED RCOSCHFCTRIMFRACT RCOSCHFCTR SPARE2
IMFRACT_EN
R/W-X R/W-X R/W-X R/W-X
15 14 13 12 11 10 9 8
SPARE2
R/W-X
7 6 5 4 3 2 1 0
SPARE2 XOSC_HF_FAST_START
R/W-X R/W-X
Table 6-87. CTL1 Register Field Descriptions
Bit Field Type Reset Description
31-23 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
22-18 RCOSCHFCTRIMFRACT R/W X
Internal. Only to be used through TI provided API.
17 RCOSCHFCTRIMFRACT R/W X
Internal. Only to be used through TI provided API.
_EN
16-2 SPARE2 R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
1-0 XOSC_HF_FAST_START R/W X
Internal. Only to be used through TI provided API.
512
Power, Reset, and Clock Management SWCU117A–February 2015–Revised March 2015
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