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Table 6-86. CTL0 Register Field Descriptions (continued)
Bit Field Type Reset Description
15-13 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
12 RCOSC_LF_TRIMMED R/W X
Internal. Only to be used through TI provided API.
11 XOSC_HF_POWER_MO R/W X
Internal. Only to be used through TI provided API.
DE
10 XOSC_LF_DIG_BYPASS R/W X
Bypass XOSC_LF and use the digital input clock from AON for the
xosc_lf clock.. 0: Use 32kHz XOSC as xosc_lf clock source 1: Use
digital input (from AON) as xosc_lf clock source. This bit will only
have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf as
the sclk_lf source. The muxing performed by this bit is not glitch free.
The following procedure should be followed when changing this field
to avoid glitches on sclk_lf.. 1) Set SCLK_LF_SRC_SEL to select
any source other than the xosc_lf clock source. 2) Set or clear this
bit to bypass or not bypass the xosc_lf. 3) Set SCLK_LF_SRC_SEL
to use xosc_lf. It is recommended that either the rcosc_hf or xosc_hf
(whichever is currently active) be selected as the source in step 1
above. This provides a faster clock change.
9 CLK_LOSS_EN R/W X
Enable clock loss circuit and hence the indicators to system
controller. Checks both SCLK_HF and SCLK_LF clock loss
indicators. 0: Disable 1: Enable Clock loss detection should be
disabled when changing the sclk_lf source. STAT0.SCLK_LF_SRC
can be polled to determine when a change to a new sclk_lf source
has completed.
8-7 ACLK_TDC_SRC_SEL R/W X
Source select for aclk_tdc. 00: RCOSC_HF (48MHz) 01:
RCOSC_HF (24MHz) 10: XOSC_HF (24MHz) 11: Not used
6-5 ACLK_REF_SRC_SEL R/W X
Source select for aclk_ref 00: RCOSC_HF desirved (31.25kHz) 01:
XOSC_HF derived (31.25kHz) 10: RCOSC_LF (32kHz) 11:
XOSC_LF (32.768kHz)
4 SPARE4 R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
3-2 SCLK_LF_SRC_SEL R/W X
Source select for sclk_lf
0h = Low frequency clock derived from High Frequency RCOSC
1h = Low frequency clock derived from High Frequency XOSC
2h = Low frequency RCOSC
3h = Low frequency XOSC
1 SCLK_MF_SRC_SEL R/W X
Internal. Only to be used through TI provided API.
0h = Internal. Only to be used through TI provided API.
1h = Medium frequency clock derived from high frequency XOSC.
0 SCLK_HF_SRC_SEL R/W X
Source select for sclk_hf
0h = High frequency RCOSC clk
1h = High frequency XOSC clk
511
SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management
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