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Cortex-M3 Processor Registers

2.7.1 CPU_ITM Registers

Table 2-26 lists the memory-mapped registers for the CPU_ITM. All register offset addresses not listed in

Table 2-26 should be considered as reserved locations and the register contents should not be modified.

Table 2-26. CPU_ITM Registers

Offset Acronym Register Name Section

0h STIM0 Stimulus Port 0 Section 2.7.1.1

4h STIM1 Stimulus Port 1 Section 2.7.1.2

8h STIM2 Stimulus Port 2 Section 2.7.1.3

Ch STIM3 Stimulus Port 3 Section 2.7.1.4

10h STIM4 Stimulus Port 4 Section 2.7.1.5

14h STIM5 Stimulus Port 5 Section 2.7.1.6

18h STIM6 Stimulus Port 6 Section 2.7.1.7

1Ch STIM7 Stimulus Port 7 Section 2.7.1.8

20h STIM8 Stimulus Port 8 Section 2.7.1.9

24h STIM9 Stimulus Port 9 Section 2.7.1.10

28h STIM10 Stimulus Port 10 Section 2.7.1.11

2Ch STIM11 Stimulus Port 11 Section 2.7.1.12

30h STIM12 Stimulus Port 12 Section 2.7.1.13

34h STIM13 Stimulus Port 13 Section 2.7.1.14

38h STIM14 Stimulus Port 14 Section 2.7.1.15

3Ch STIM15 Stimulus Port 15 Section 2.7.1.16

40h STIM16 Stimulus Port 16 Section 2.7.1.17

44h STIM17 Stimulus Port 17 Section 2.7.1.18

48h STIM18 Stimulus Port 18 Section 2.7.1.19

4Ch STIM19 Stimulus Port 19 Section 2.7.1.20

50h STIM20 Stimulus Port 20 Section 2.7.1.21

54h STIM21 Stimulus Port 21 Section 2.7.1.22

58h STIM22 Stimulus Port 22 Section 2.7.1.23

5Ch STIM23 Stimulus Port 23 Section 2.7.1.24

60h STIM24 Stimulus Port 24 Section 2.7.1.25

64h STIM25 Stimulus Port 25 Section 2.7.1.26

68h STIM26 Stimulus Port 26 Section 2.7.1.27

6Ch STIM27 Stimulus Port 27 Section 2.7.1.28

70h STIM28 Stimulus Port 28 Section 2.7.1.29

74h STIM29 Stimulus Port 29 Section 2.7.1.30

78h STIM30 Stimulus Port 30 Section 2.7.1.31

7Ch STIM31 Stimulus Port 31 Section 2.7.1.32

E00h TER Trace Enable Section 2.7.1.33

E40h TPR Trace Privilege Section 2.7.1.34

E80h TCR Trace Control Section 2.7.1.35

FB0h LAR Lock Access Section 2.7.1.36

FB4h LSR Lock Status Section 2.7.1.37

SWCU117A–February 2015–Revised March 2015

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