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PRCM Registers

6.2.4 DDI_0_OSC Registers

Table 6-85 lists the memory-mapped registers for the DDI_0_OSC. All register offset addresses not listed

in Table 6-85 should be considered as reserved locations and the register contents should not be

modified.

Table 6-85. DDI_0_OSC Registers

Offset Acronym Register Name Section

0h CTL0 Control 0 Section 6.2.4.1

4h CTL1 Control 1 Section 6.2.4.2

8h RADCEXTCFG RADC External Configuration Section 6.2.4.3

Ch AMPCOMPCTL Amplitude Compensation Control Section 6.2.4.4

10h AMPCOMPTH1 Amplitude Compensation Threashold 1 Section 6.2.4.5

14h AMPCOMPTH2 Amplitude Compensation Threashold 2 Section 6.2.4.6

18h ANABYPASSVAL1 Analog Bypass Values 1 Section 6.2.4.7

1Ch ANABYPASSVAL2 Analog Bypass Values 2 Section 6.2.4.8

20h ATESTCTL Analog Test Control Section 6.2.4.9

24h ADCDOUBLERNANOAMPCTL ADC Doubler Nanoamp Control Section 6.2.4.10

28h XOSCHFCTL XOSCHF Control Section 6.2.4.11

2Ch LFOSCCTL Low Frequency Oscillator Control Section 6.2.4.12

30h RCOSCHFCTL RCOSCHF Control Section 6.2.4.13

34h STAT0 Status 0 Section 6.2.4.14

38h STAT1 Status 1 Section 6.2.4.15

3Ch STAT2 Status 2 Section 6.2.4.16

509

SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management

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