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PRCM Registers

6.2.3.11 RECHARGESTAT Register (Offset = 34h) [reset = X]

RECHARGESTAT is shown in Figure 17-46 and described in Table 17-67.

Recharge Controller Status This register controls various status registers which are updated during

recharge. The register is mostly intended for test and debug.

Figure 6-77. RECHARGESTAT Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED VDDR_SMPLS

R-X R-X

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MAX_USED_PER

R/W-X

Table 6-81. RECHARGESTAT Register Field Descriptions

Bit Field Type Reset Description

31-20 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

19-16 VDDR_SMPLS R X

The last 4 VDDR samples, bit 0 being the newest. The register is

being updated in every recharge period with a shift left, and bit 0 is

updated with the last VDDR sample, ie a 1 is shiftet in in case VDDR

> VDDR_threshold just before recharge starts. Otherwise a 0 will be

shifted in.

15-0 MAX_USED_PER R/W X

The maximum value of recharge period seen with VDDR>threshold.

The VDDR voltage is compared against the threshold voltage at just

before each recharge. If VDDR is above threshold,

MAX_USED_PER is updated with max ( current recharge peride;

MAX_USED_PER ) This way MAX_USED_PER can track the

recharge period where VDDR is decharged to the threshold value.

We can therefore use the value as an indication of the leakage

current during recharge. This bitfield is cleared to 0 when writing this

505

SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management

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