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Cortex-M3 Processor Registers

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Table 2-25. Cortex-M3 Instruction Summary (continued)

Mnemonic Operands Brief Description Flags

STRH, STRHT Rt, [Rn {, #offset}] Store register halfword –

STRSB, STRSBT Rt, [Rn {, #offset}] Store register signed byte –

STRSH, STRSHT Rt, [Rn {, #offset}] Store register signed halfword –

STRT Rt, [Rn {, #offset}] Store register word –

SUB, SUBS {Rd,} Rn, Op2 Subtract N, Z, C, V

SUB, SUBW {Rd,} Rn, #imm12 Subtract 12-bit constant N, Z, C, V

SVC #imm Supervisor call –

SXTB {Rd,} Rm {,ROR #n} Sign extend a byte –

SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword –

TBB [Rn, Rm] Table branch byte –

TBH [Rn, Rm, LSL #1] Table branch halfword –

TEQ Rn, Op2 Test equivalence N, Z, C

TST Rn, Op2 Test N, Z, C

UBFX Rd, Rn, #lsb, #width Unsigned bit field extract –

UDIV {Rd,} Rn, Rm Unsigned divide –

Unsigned multiply with

UMLAL RdLo, RdHi, Rn, Rm accumulate (32 × 32 + 32 + –

32), 64-bit result

Unsigned multiply (32 × 2), 64-

UMULL RdLo, RdHi, Rn, Rm –

bit result

USAT Rd, #n, Rm {,shift #s} Unsigned saturate Q

UXTB {Rd,} Rm, {,ROR #n} Zero extend a byte –

UXTH {Rd,} Rm, {,ROR #n} Zero extend a halfword –

USAT Rd, #n, Rm {,shift #s} Unsigned saturate Q

UXTB {Rd,} Rm {,ROR #n} Zero extend a byte –

UXTH {Rd,} Rm {,ROR #n} Zero extend a halfword –

WFE – Wait for event –

WFI – Wait for interrupt –

2.7 Cortex-M3 Processor Registers

SWCU117A–February 2015–Revised March 2015

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