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PRCM Registers

6.2.3.4 AUXCFG Register (Offset = Ch) [reset = X]

AUXCFG is shown in Figure 17-39 and described in Table 17-60.

AUX Configuration This register contains power management related signals for the AUX domain.

Figure 6-70. AUXCFG Register

31 30 29 28 27 26 25 24

RESERVED

R/W-X

23 22 21 20 19 18 17 16

RESERVED

R/W-X

15 14 13 12 11 10 9 8

RESERVED

R/W-X

7 6 5 4 3 2 1 0

RESERVED RAM_RET_EN

R/W-X R/W-1h

Table 6-74. AUXCFG Register Field Descriptions

Bit Field Type Reset Description

31-1 RESERVED R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

0 RAM_RET_EN R/W 1h

This bit controls retention mode for the AUX_RAM:BANK0: 0:

Retention is disabled 1: Retention is enabled NB: If retention is

disabled, the AUX_RAM will be powered off when it would otherwise

be put in retention mode

497

SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management

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