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PRCM Registers

6.2.3 AON_WUC Registers

Table 17-56 lists the memory-mapped registers for the AON_WUC. All register offset addresses not listed

in Table 17-56 should be considered as reserved locations and the register contents should not be

modified.

Table 6-70. AON_WUC Registers

Offset Acronym Register Name Section

0h MCUCLK MCU Clock Management Section 17.8.4.1

4h AUXCLK AUX Clock Management Section 17.8.4.2

8h MCUCFG MCU Configuration Section 17.8.4.3

Ch AUXCFG AUX Configuration Section 17.8.4.4

10h AUXCTL AUX Control Section 17.8.4.5

14h PWRSTAT Power Status Section 17.8.4.6

18h SHUTDOWN Shutdown Control Section 17.8.4.7

20h CTL0 Control 0 Section 17.8.4.8

24h CTL1 Control 1 Section 17.8.4.9

30h RECHARGECFG Recharge Controller Configuration Section 17.8.4.10

34h RECHARGESTAT Recharge Controller Status Section 17.8.4.11

38h OSCCFG Oscillator Configuration Section 17.8.4.12

40h JTAGCFG JTAG Configuration Section 17.8.4.13

44h JTAGUSERCODE JTAG USERCODE Section 17.8.4.14

493

SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management

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