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Instruction Set Summary
Table 2-25. Cortex-M3 Instruction Summary (continued)
Mnemonic Operands Brief Description Flags
LSR, LSRS Rd, Rm, <Rs|#n> Logical shift right N, Z, C
Multiply with accumulate, 32-bit
MLA Rd, Rn, Rm, Ra –
result
Multiply and subtract, 32-bit
MLS Rd, Rn, Rm, Ra –
result
MOV, MOVS Rd, Op2 Move N, Z, C
MOV, MOVW Rd, #imm16 Move 16-bit constant N, Z, C
MOVT Rd, #imm16 Move top –
Move from special register to
MRS Rd, spec_reg –
general register
Move from general register to
MSR spec_reg, Rm N, Z, C, V
special register
MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result N, Z
MVN, MVNS Rd, Op2 Move NOT N, Z, C
NOP – No operation –
ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N, Z, C
ORR, ORRS {Rd,} Rn, Op2 Logical OR N, Z, C
POP reglist Pop registers from stack –
PUSH reglist Push registers onto stack –
RBIT Rd, Rn Reverse bits –
REV Rd, Rn Reverse byte order in a word –
Reverse byte order in each
REV16 Rd, Rn –
halfword
Reverse byte order in bottom
REVSH Rd, Rn –
halfword and sign extend
ROR, RORS Rd, Rm, <Rs|#n> Rotate right N, Z, C
RRX, RRXS Rd, Rm Rotate right with extend N, Z, C
RSB, RSBS {Rd,} Rn, Op2 Reverse subtract N, Z, C, V
SBC, SBCS {Rd,} Rn, Op2 Subtract with carry N, Z, C, V
SBFX Rd, Rn, #lsb, #width Signed bit field extract –
SDIV {Rd,} Rn, Rm Signed divide –
SEV – Send event –
Signed multiply with
SMLAL RdLo, RdHi, Rn, Rm accumulate (32 × 32 + 64), 64- –
bit result
Signed multiply (32 × 32), 64-
SMULL RdLo, RdHi, Rn, Rm –
bit result
SSAT Rd, #n, Rm {,shift #s} Signed saturate Q
Store multiple registers,
STM Rn{!}, reglist –
increment after
Store multiple registers,
STMDB, STMEA Rn{!}, reglist –
decrement before
Store multiple registers,
STMFD, STMIA Rn{!}, reglist –
increment after
STR Rt, [Rn {, #offset}] Store register word –
STRB, STRBT Rt, [Rn {, #offset}] Store register byte –
STRD Rt, Rt2, [Rn {, #offset}] Store register two words –
STREX Rt, Rt, [Rn {, #offset}] Store register exclusive –
STREXB Rd, Rt, [Rn] Store register exclusive byte –
Store register exclusive
STREXH Rd, Rt, [Rn] –
halfword
49
SWCU117A–February 2015–Revised March 2015
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