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PRCM Registers

6.2.1.56 RAMRETEN Register (Offset = 224h) [reset = X]

RAMRETEN is shown in Figure 6-62 and described in Table 6-64.

Memory Retention Control

Figure 6-62. RAMRETEN Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

R-X

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED RFC VIMS

R-X R/W-X R/W-3h

Table 6-64. RAMRETEN Register Field Descriptions

Bit Field Type Reset Description

31-3 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

2 RFC R/W X

0: Retention for RFC SRAM disabled 1: Retention for RFC SRAM

enabled

1-0 VIMS R/W 3h

0: Memory retention disabled 1: Memory retention enabled Bit 0:

VIMS_TRAM Bit 1: VIMS_CRAM Legal modes depend on settings in

VIMS:CTL.MODE 00: VIMS:CTL.MODE must be OFF before

DEEPSLEEP is asserted - must be set to CACHE or SPLIT mode

after waking up again 01: VIMS:CTL.MODE must be GPRAM before

DEEPSLEEP is asserted. Must remain in GPRAM mode after wake

up, alternatively select OFF mode first and then CACHE or SPILT

mode. 10: Illegal mode 11: No restrictions

485

SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management

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