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PRCM Registers

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6.2.1.53 PDSTAT1CPU Register (Offset = 1A0h) [reset = X]

PDSTAT1CPU is shown in Figure 6-59 and described in Table 6-61.

CPU Power Domain Status

Figure 6-59. PDSTAT1CPU Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

R-X

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED ON

R-X R-1h

Table 6-61. PDSTAT1CPU Register Field Descriptions

Bit Field Type Reset Description

31-1 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

0 ON R 1h

This is an alias for PDSTAT1.CPU_ON

482

Power, Reset, and Clock Management SWCU117A–February 2015–Revised March 2015

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