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Instruction Set Summary

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Table 2-25. Cortex-M3 Instruction Summary

Mnemonic Operands Brief Description Flags

ADC, ADCS {Rd,} Rn, Op2 Add with carry N, Z, C, V

ADD, ADDS {Rd,} Rn, Op2 Add N, Z, C, V

ADD, ADDW {Rd,} Rn , #imm12 Add N, Z, C, V

ADR Rd, label Load PC-relative address –

AND, ANDS {Rd,} Rn, Op2 Logical AND N, Z, C

ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic shift right N, Z, C

B label Branch –

BFC Rd, #lsb, #width Bit field clear –

BFI Rd, Rn, #lsb, #width Bit field insert –

BIC, BICS {Rd,} Rn, Op2 Bit clear N, Z, C

BKPT #imm Breakpoint –

BL label Branch with link –

BLX Rm Branch indirect with link –

BX Rm Branch indirect –

Compare and branch if

CBNZ Rn, label –

nonzero

CBZ Rn, label Compare and branch if zero –

CLREX – Clear exclusive –

CLZ Rd, Rm Count leading zeros –

CMN Rn, Op2 Compare negative N, Z, C, V

CMP Rn, Op2 Compare N, Z, C, V

Change processor state,

CPSID i –

disable interrupts

Change processor state,

CPSIE i –

enable interrupts

DMB – Data memory barrier –

DSB – Data synchronization barrier –

EOR, EORS {Rd,} Rn, Op2 Exclusive OR N, Z, C

Instruction synchronization

ISB – –

barrier

IT – If‑Then condition block –

Load multiple registers,

LDM Rn{!}, reglist –

increment after

Load multiple registers,

LDMDB, LDMEA Rn{!}, reglist –

decrement before

Load multiple registers,

LDMFD, LDMIA Rn{!}, reglist –

increment after

LDR Rt, [Rn, #offset] Load register with word –

LDRB, LDRBT Rt, [Rn, #offset] Load register with byte –

LDRD Rt, Rt2, [Rn, #offset] Load register with 2 bytes –

LDREX Rt, [Rn, #offset] Load register exclusive –

Load register exclusive with

LDREXB Rt, [Rn] –

byte

Load register exclusive with

LDREXH Rt, [Rn] –

halfword

LDRH, LDRHT Rt, [Rn, #offset] Load register with halfword –

LDRSB, LDRSBT Rt, [Rn, #offset] Load register with signed byte –

Load register with signed

LDRSH, LDRSHT Rt, [Rn, #offset] –

halfword

LDRT Rt, [Rn, #offset] Load register with word –

LSL, LSLS Rd, Rm, <Rs|#n> Logical shift left N, Z, C

SWCU117A–February 2015–Revised March 2015

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