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6.2.1.50 PDSTAT1 Register (Offset = 194h) [reset = X]
PDSTAT1 is shown in Figure 6-56 and described in Table 6-58.
Power Domain Status
Figure 6-56. PDSTAT1 Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED BUS_ON VIMS_MODE RFC_ON CPU_ON RESERVED
R-X R-1h R-1h R-X R-1h R-X
Table 6-58. PDSTAT1 Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
4 BUS_ON R 1h
0: BUS domain not accessible 1: BUS domain is currently accessible
3 VIMS_MODE R 1h
0: VIMS domain not accessible 1: VIMS domain is currently
accessible
2 RFC_ON R X
0: RFC domain not accessible 1: RFC domain is currently accessible
1 CPU_ON R 1h
0: CPU and BUS domain not accessible 1: CPU and BUS domains
are both currently accessible
0 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
479
SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management
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