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6.2.1.46 PDCTL1 Register (Offset = 17Ch) [reset = X]
PDCTL1 is shown in Figure 6-52 and described in Table 6-54.
Power Domain Control
Figure 6-52. PDCTL1 Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED RESERVED VIMS_MODE RFC_ON CPU_ON RESERVED
R-X R/W-X R/W-1h R/W-X R/W-1h R-X
Table 6-54. PDCTL1 Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
4 RESERVED R/W X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
3 VIMS_MODE R/W 1h
0: VIMS power domain is only powered when CPU power domain is
powered. 1: VIMS power domain is powered whenever the BUS
power domain is powered.
2 RFC_ON R/W X
0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 1:
RFC power domain powered on Bit shall be used by RFC in
autonomus mode but there is no HW restrictions fom system CPU to
access the bit.
1 CPU_ON R/W 1h
0: Causes a power down of the CPU power domain when system
CPU indicates it is idle. 1: Initiates power-on of the CPU power
domain. This bit is automatically set by a WIC power-on event.
0 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
475
SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management
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