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PRCM Registers

6.2.1.40 PDCTL0SERIAL Register (Offset = 134h) [reset = X]

PDCTL0SERIAL is shown in Figure 6-46 and described in Table 6-48.

SERIAL Power Domain Control

Figure 6-46. PDCTL0SERIAL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

R-X

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED ON

R-X R/W-X

Table 6-48. PDCTL0SERIAL Register Field Descriptions

Bit Field Type Reset Description

31-1 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

0 ON R/W X

Alias for PDCTL0.SERIAL_ON

469

SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management

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