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PRCM Registers

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6.2.1.35 I2SWCLKDIV Register (Offset = DCh) [reset = X]

I2SWCLKDIV is shown in Figure 6-41 and described in Table 6-43.

WCLK Division Ratio

Figure 6-41. I2SWCLKDIV Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED WDIV

R-X R/W-X

Table 6-43. I2SWCLKDIV Register Field Descriptions

Bit Field Type Reset Description

31-16 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

15-0 WDIV R/W X

If I2SCLKCTL.WCLK_PHASE = 0, Single phase. WCLK is high one

BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK periods.

WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz] MCUCLK is 48MHz

in normal mode. For powerdown mode the frequency is defined by

AON_WUC:MCUCLK.PWR_DWN_SRC If

I2SCLKCTL.WCLK_PHASE = 1, Dual phase. Each phase on WCLK

(50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK periods.

WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz] If

I2SCLKCTL.WCLK_PHASE = 2, User defined. WCLK is high

WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8]

(unsigned, [1-255]) BCLK periods. WCLK = MCUCLK /

(BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] For changes to take effect,

CLKLOADCTL.LOAD needs to be written

464

Power, Reset, and Clock Management SWCU117A–February 2015–Revised March 2015

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