User manual

www.ti.com

PRCM Registers

6.2.1.34 I2SBCLKDIV Register (Offset = D8h) [reset = X]

I2SBCLKDIV is shown in Figure 6-40 and described in Table 6-42.

BCLK Division Ratio

Figure 6-40. I2SBCLKDIV Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED BDIV

R-X R/W-X

Table 6-42. I2SBCLKDIV Register Field Descriptions

Bit Field Type Reset Description

31-10 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

9-0 BDIV R/W X

An unsigned factor of the division ratio used to generate I2S BCLK

[2-1024]: BCLK = MCUCLK/BDIV[Hz] MCUCLK is 48MHz in normal

mode. For powerdown mode the frequency is defined by

AON_WUC:MCUCLK.PWR_DWN_SRC A value of 0 is interpreted

as 1024. A value of 1 is invalid. If BDIV is odd and

I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock

is one MCUCLK period longer than the high phase. If BDIV is odd

and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the

clock is one MCUCLK period longer than the low phase. For

changes to take effect, CLKLOADCTL.LOAD needs to be written

463

SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management

Submit Documentation Feedback