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PRCM Registers

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6.2.1.33 I2SMCLKDIV Register (Offset = D4h) [reset = X]

I2SMCLKDIV is shown in Figure 6-39 and described in Table 6-41.

MCLK Division Ratio

Figure 6-39. I2SMCLKDIV Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED MDIV

R-X R/W-X

Table 6-41. I2SMCLKDIV Register Field Descriptions

Bit Field Type Reset Description

31-10 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

9-0 MDIV R/W X

An unsigned factor of the division ratio used to generate MCLK [2-

1024]: MCLK = MCUCLK/MDIV[Hz] MCUCLK is 48MHz in normal

mode. For powerdown mode the frequency is defined by

AON_WUC:MCUCLK.PWR_DWN_SRC A value of 0 is interpreted

as 1024. A value of 1 is invalid. If MDIV is odd the low phase of the

clock is one MCUCLK period longer than the high phase. For

changes to take effect, CLKLOADCTL.LOAD needs to be written

462

Power, Reset, and Clock Management SWCU117A–February 2015–Revised March 2015

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