User manual

Coretex-M3 Core Registers

www.ti.com

2.5.2.20 Base Priority Mask Register (BASEPRI)

Table 2-23. Base Priority Mask Register (BASEPRI)

Address Offset Reset 0x0000 0000

Physical Address Instance

Description

The Base Priority Mask BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value,

it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. Exceptions must be disabled when

they might impact the timing of critical tasks. This register is accessible only in privileged mode. For more information on exception priority

levels, see Section 4.1.2, Exception Types.

Type R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED BASEPRI RESERVED

Bits Field Name Description Type Reset

31:8 RESERVED Reserved RO 0x0000 00

7:5 BASEPRI Base Priority R/W 0x0

Any exception that has a programmable priority level with the same

or lower priority as the value of this field is masked. The PRIMASK

priority levels. Higher priority exceptions have lower priority levels.

Value Description

0x0 All exceptions are unmasked.

0x1 All exceptions with priority levels 1–7 are masked.

0x2 All exceptions with priority levels 2–7 are masked.

0x3 All exceptions with priority levels 3–7 are masked.

0x4 All exceptions with priority levels 4–7 are masked.

0x5 All exceptions with priority levels 5–7 are masked.

0x6 All exceptions with priority levels 6 and 7 are masked.

0x7 All exceptions with priority level 7 are masked.

4:0 RESERVED Reserved RO 0x0

SWCU117A–February 2015–Revised March 2015

Submit Documentation Feedback