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PRCM Registers

6.2.1.30 I2SBCLKSEL Register (Offset = C8h) [reset = X]

I2SBCLKSEL is shown in Figure 6-36 and described in Table 6-38.

I2S Clock Control

Figure 6-36. I2SBCLKSEL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SPARE

R/W-X

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPARE SRC

R/W-X R/W-X

Table 6-38. I2SBCLKSEL Register Field Descriptions

Bit Field Type Reset Description

31-1 SPARE R/W X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

0 SRC R/W X

BCLK source selector 0: Use external BCLK 1: Use internally

generated clock For changes to take effect, CLKLOADCTL.LOAD

needs to be written

459

SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management

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