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PRCM Registers

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6.2.1.29 CPUCLKDIV Register (Offset = B8h) [reset = X]

CPUCLKDIV is shown in Figure 6-35 and described in Table 6-37.

Internal. Only to be used through TI provided API.

Figure 6-35. CPUCLKDIV Register

31 30 29 28 27 26 25 24

RESERVED

R-X

23 22 21 20 19 18 17 16

RESERVED

R-X

15 14 13 12 11 10 9 8

RESERVED

R-X

7 6 5 4 3 2 1 0

RESERVED RATIO

R-X R/W-X

Table 6-37. CPUCLKDIV Register Field Descriptions

Bit Field Type Reset Description

31-1 RESERVED R X

Internal. Only to be used through TI provided API.

0 RATIO R/W X

Internal. Only to be used through TI provided API.

0h = Internal. Only to be used through TI provided API.

1h = Internal. Only to be used through TI provided API.

458

Power, Reset, and Clock Management SWCU117A–February 2015–Revised March 2015

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