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PRCM Registers

6.2.1.14 GPTCLKGR Register (Offset = 54h) [reset = X]

GPTCLKGR is shown in Figure 6-20 and described in Table 6-22.

GPT Clock Gate For Run Mode

Figure 6-20. GPTCLKGR Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

R-X

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CLK_EN

R-X R/W-X

Table 6-22. GPTCLKGR Register Field Descriptions

Bit Field Type Reset Description

31-4 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

3-0 CLK_EN R/W X

Each bit below has the following meaning: 0: Disable clock 1: Enable

clock ENUMs can be combined For changes to take effect,

CLKLOADCTL.LOAD needs to be written

1h = Enable clock for GPT0

2h = Enable clock for GPT1

4h = Enable clock for GPT2

8h = Enable clock for GPT3

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SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management

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