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6.2.1.10 SECDMACLKGDS Register (Offset = 44h) [reset = X]
SECDMACLKGDS is shown in Figure 6-16 and described in Table 6-18.
TRNG, CRYPTO And UDMA Clock Gate For Deep Sleep Mode
Figure 6-16. SECDMACLKGDS Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED DMA_CLK_EN
R-X R/W-X
7 6 5 4 3 2 1 0
RESERVED TRNG_CLK_E CRYPTO_CLK
N _EN
R-X R/W-X R/W-X
Table 6-18. SECDMACLKGDS Register Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
8 DMA_CLK_EN R/W X
0: Disable clock 1: Enable clock For changes to take effect,
CLKLOADCTL.LOAD needs to be written
7-2 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
1 TRNG_CLK_EN R/W X
0: Disable clock 1: Enable clock For changes to take effect,
CLKLOADCTL.LOAD needs to be written
0 CRYPTO_CLK_EN R/W X
0: Disable clock 1: Enable clock For changes to take effect,
CLKLOADCTL.LOAD needs to be written
439
SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management
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