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PRCM Registers

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6.2.1.7 VIMSCLKG Register (Offset = 30h) [reset = X]

VIMSCLKG is shown in Figure 6-13 and described in Table 6-15.

VIMS Clock Gate

Figure 6-13. VIMSCLKG Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

R-X

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED CLK_EN

R-X R/W-3h

Table 6-15. VIMSCLKG Register Field Descriptions

Bit Field Type Reset Description

31-2 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

1-0 CLK_EN R/W 3h

00: Disable clock 01: Disable clock when SYSBUS clock is disabled

11: Enable clock For changes to take effect, CLKLOADCTL.LOAD

needs to be written

436

Power, Reset, and Clock Management SWCU117A–February 2015–Revised March 2015

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