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6.2.1.5 CLKLOADCTL Register (Offset = 28h) [reset = X]
CLKLOADCTL is shown in Figure 6-11 and described in Table 6-13.
Clock Load Control
Figure 6-11. CLKLOADCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED LOAD_DONE LOAD
R-X R-1h W-X
Table 6-13. CLKLOADCTL Register Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
1 LOAD_DONE R 1h
Status of LOAD. Will be cleared to 0 when any of the registers
requiring a LOAD is written to, and be set to 1 when a LOAD is
done. Note that writing no change to a register will result in the
LOAD_DONE being cleared. 0 : One or more registers have been
write accessed after last LOAD 1 : No registers are write accessed
after last LOAD
0 LOAD W X
0: No action 1: Load settings to CLKCTRL. Bit is HW cleared.
Multiple changes to settings may be done before LOAD is written
once so all changes takes place at the same time. LOAD can also
be done after single setting updates. Registers that needs to be
followed by LOAD before settings being applied are: - RFCCLKG -
VIMSCLKG - SECDMACLKGR - SECDMACLKGS -
SECDMACLKGDS - GPIOCLKGR - GPIOCLKGS - GPIOCLKGDS -
GPTCLKGR - GPTCLKGS - GPTCLKGDS - GPTCLKDIV -
I2CCLKGR - I2CCLKGS - I2CCLKGDS - SSICLKGR - SSICLKGS -
SSICLKGDS - UARTCLKGR - UARTCLKGS - UARTCLKGDS -
I2SCLKGR - I2SCLKGS - I2SCLKGDS - I2SBCLKSEL - I2SCLKCTL
- I2SMCLKDIV - I2SBCLKDIV - I2SWCLKDIV - RAMHWOPT
434
Power, Reset, and Clock Management SWCU117A–February 2015–Revised March 2015
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