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PRCM Registers

6.2.1.2 INFRCLKDIVS Register (Offset = 4h) [reset = X]

INFRCLKDIVS is shown in Figure 6-8 and described in Table 6-10.

Infrastructure Clock Division Factor For Sleep Mode

Figure 6-8. INFRCLKDIVS Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESERVED

R-X

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED RATIO

R-X R/W-X

Table 6-10. INFRCLKDIVS Register Field Descriptions

Bit Field Type Reset Description

31-2 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

1-0 RATIO R/W X

Division rate for clocks driving modules in the MCU_AON domain

when system CPU is in sleep mode. Division ratio affects both

infrastructure clock and perbusull clock.

0h = Divide by 1

1h = Divide by 2

2h = Divide by 8

3h = Divide by 32

431

SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management

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