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Table 6-8. PRCM Registers (continued)
Offset Acronym Register Name Section
140h PDSTAT0 Power Domain Status Section 6.2.1.42
144h PDSTAT0RFC RFC Power Domain Status Section 6.2.1.43
148h PDSTAT0SERIAL SERIAL Power Domain Status Section 6.2.1.44
14Ch PDSTAT0PERIPH PERIPH Power Domain Status Section 6.2.1.45
17Ch PDCTL1 Power Domain Control Section 6.2.1.46
184h PDCTL1CPU CPU Power Domain Control Section 6.2.1.47
188h PDCTL1RFC RFC Power Domain Control Section 6.2.1.48
18Ch PDCTL1VIMS VIMS Power Domain Control Section 6.2.1.49
194h PDSTAT1 Power Domain Status Section 6.2.1.50
198h PDSTAT1BUS BUS Power Domain Status Section 6.2.1.51
19Ch PDSTAT1RFC RFC Power Domain Status Section 6.2.1.52
1A0h PDSTAT1CPU CPU Power Domain Status Section 6.2.1.53
1A4h PDSTAT1VIMS VIMS Power Domain Status Section 6.2.1.54
1D0h RFCMODESEL Selected RFC Mode Section 6.2.1.55
224h RAMRETEN Memory Retention Control Section 6.2.1.56
250h RAMHWOPT CONFIG SIZE For SRAM Section 6.2.1.57
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SWCU117A–February 2015–Revised March 2015 Power, Reset, and Clock Management
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