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PRCM Registers

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6.2.1 PRCM Registers

Table 6-8 lists the memory-mapped registers for the PRCM. All register offset addresses not listed in

Table 6-8 should be considered as reserved locations and the register contents should not be modified.

Table 6-8. PRCM Registers

Offset Acronym Register Name Section

0h INFRCLKDIVR Infrastructure Clock Division Factor For Run Mode Section 6.2.1.1

4h INFRCLKDIVS Infrastructure Clock Division Factor For Sleep Mode Section 6.2.1.2

8h INFRCLKDIVDS Infrastructure Clock Division Factor For DeepSleep Section 6.2.1.3

Mode

Ch VDCTL MCU Voltage Domain Control Section 6.2.1.4

28h CLKLOADCTL Clock Load Control Section 6.2.1.5

2Ch RFCCLKG RFC Clock Gate Section 6.2.1.6

30h VIMSCLKG VIMS Clock Gate Section 6.2.1.7

3Ch SECDMACLKGR TRNG, CRYPTO And UDMA Clock Gate For Run Section 6.2.1.8

Mode

40h SECDMACLKGS TRNG, CRYPTO And UDMA Clock Gate For Sleep Section 6.2.1.9

Mode

44h SECDMACLKGDS TRNG, CRYPTO And UDMA Clock Gate For Deep Section 6.2.1.10

Sleep Mode

48h GPIOCLKGR GPIO Clock Gate For Run Mode Section 6.2.1.11

4Ch GPIOCLKGS GPIO Clock Gate For Sleep Mode Section 6.2.1.12

50h GPIOCLKGDS GPIO Clock Gate For Deep Sleep Mode Section 6.2.1.13

54h GPTCLKGR GPT Clock Gate For Run Mode Section 6.2.1.14

58h GPTCLKGS GPT Clock Gate For Sleep Mode Section 6.2.1.15

5Ch GPTCLKGDS GPT Clock Gate For Deep Sleep Mode Section 6.2.1.16

60h I2CCLKGR I2C Clock Gate For Run Mode Section 6.2.1.17

64h I2CCLKGS I2C Clock Gate For Sleep Mode Section 6.2.1.18

68h I2CCLKGDS I2C Clock Gate For Deep Sleep Mode Section 6.2.1.19

6Ch UARTCLKGR UART Clock Gate For Run Mode Section 6.2.1.20

70h UARTCLKGS UART Clock Gate For Sleep Mode Section 6.2.1.21

74h UARTCLKGDS UART Clock Gate For Deep Sleep Mode Section 6.2.1.22

78h SSICLKGR SSI Clock Gate For Run Mode Section 6.2.1.23

7Ch SSICLKGS SSI Clock Gate For Sleep Mode Section 6.2.1.24

80h SSICLKGDS SSI Clock Gate For Deep Sleep Mode Section 6.2.1.25

84h I2SCLKGR I2S Clock Gate For Run Mode Section 6.2.1.26

88h I2SCLKGS I2S Clock Gate For Sleep Mode Section 6.2.1.27

8Ch I2SCLKGDS I2S Clock Gate For Deep Sleep Mode Section 6.2.1.28

B8h CPUCLKDIV CPU Clock Division Factor Section 6.2.1.29

C8h I2SBCLKSEL I2S Clock Control Section 6.2.1.30

CCh GPTCLKDIV GPT Scalar Section 6.2.1.31

D0h I2SCLKCTL I2S Clock Control Section 6.2.1.32

D4h I2SMCLKDIV MCLK Division Ratio Section 6.2.1.33

D8h I2SBCLKDIV BCLK Division Ratio Section 6.2.1.34

DCh I2SWCLKDIV WCLK Division Ratio Section 6.2.1.35

10Ch SWRESET SW Initiated Resets Section 6.2.1.36

110h WARMRESET WARM Reset Control And Status Section 6.2.1.37

12Ch PDCTL0 Power Domain Control Section 6.2.1.38

130h PDCTL0RFC RFC Power Domain Control Section 6.2.1.39

134h PDCTL0SERIAL SERIAL Power Domain Control Section 6.2.1.40

138h PDCTL0PERIPH PERIPH Power Domain Control Section 6.2.1.41

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Power, Reset, and Clock Management SWCU117A–February 2015–Revised March 2015

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