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6.1.4.1.1 Controlling the Oscillators
Figure 6-3 shows that the oscillator interface is located in AUX_PD.
For the system CPU to access the oscillator interface, perform the following steps:
• Power on AUX_PD by setting [AON_WUC:AUXCTL:AUX_FORCE_ON] = 1
• Ensure AUX_PD is powered up by checking the bit [AON_WUC:PWRSTAT:AUX_PD_ON]
• Turn on the oscillator interface clock in [AUX_WUC:MODCLKEN0: AUX_DDI0_OSC] = 1
Table 6-4. System Clocks
Clock Description Possible Sources
SCLK_LF Low-frequency clock 31.25 kHz derived from 24-MHz XTAL
Always used for AON oscillator
Available for MCU_VD and AUX_PD in 32-kHz RC oscillator
Standby 32.768-kHz XTAL oscillator
31.25 kHz derived from 48-MHz RC
oscillator
Selectable in
[DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL]
SCLK_HF High-frequency clock 48 MHz derived from 48-MHz RC
Used by MCU_VD in Active and Idle oscillator
modes 48 MHz derived from 24-MHz XTAL
Used by AUX_PD in Active mode oscillator (doubled internally)
Selectable in
[DDI_0_OSC:CTL0.SCLK_HF_SRC_SEL]
SCLK_LF_AUX Used for low-power comparator in Same as SCLK_LF
AUX_PD (COMP_B)
ACLK_ADC Used as clock source for ADC Same as SCLK_HF
ACLK_REF Used as a start or stop source for Time-to- Same sources as for SCLK_LF
Digital Converter (TDC) Selectable in
[DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL]
ACLK_TDC Used as clock for TDC 48 MHz from RC oscillator
24 MHz from RC oscillator
24 MHz from XTAL oscillator
Selectable in
[DDI_0_OSC:CTL0.ACLK_TDC_SRC_SE
L]
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Power, Reset, and Clock Management SWCU117A–February 2015–Revised March 2015
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