User manual

MCU_VD
CPU_PD
System CPU
JTAG DAP
DMA controller
CRYPTO core
True random number gen.
GPT [3:0]
GPIO
SSI1
I2S
PERIPH_PD
PRCM
Wakeup interrupt controller
Event fabric
I/O controller
Watchdog timer
AON interface
MCU_AON
BUS_PD
VIMS_PD
SERIAL_PD
RFCORE_PD
UART
SSI0
I C
2
FLASH
ROM
FLASH cache
OTP/EFUSE
Interconnect
System SRAM
Radio doorbell
Radio timer
Cortex-M0 CPU
RFCORE SRAM
ROM
Radio register banks
AON_VD
JTAG_PD
ICEPick JTAG router
IEEE1149.7 (cJTAG)
Sensor processor
Oscillator interface
I/O controller
Analog interface
TDC
Timers
AUX_PD
SC SRAM
I/O Controller
Edge detect
AON IO mux
I/O state holder
Power
SYS CTL
MCU Wakeup
AUX Wakeup
Event
Event fabric
Peripherals
RTC
AON
Voltage domain
Always-on logic
Power domain
Module with retention
Module no retention
Memory
Legend
Introduction www.ti.com
Figure 6-3. Digital Power Partitioning in CC26xx
416
Power, Reset, and Clock Management SWCU117A–February 2015–Revised March 2015
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