User manual
ICEMelter™
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Table 5-22. Reset Control
Value Command Description
Reset operates under the normal control of the application or
000 Normal Operation
device controls.
The module(s) controlled by this secondary TAP will remain in
Wait in reset
001 the reset state once the reset has been asserted. This bit alone
(Extend reset)
does not reset the processor.
010 Reserved Reserved
011 Reserved Reserved
1xx Cancel Cancels reset command lockout
5.4 ICEMelter™
ICEMelter wakes up the JTAG power domain, that contains ICEPick and cJTAG modules and monitors
the activities on the TCK-pin. When ICEMelter detects traffic on the TCK-pin (8 rising edges and 8 falling
edges on TCK), it sends a power-up request to AON WUC that powers up the JTAG power domain. The
emulator must allow power-up time of at least 200 µ for JTAG power domain before sending remaining
commands to JTAG interface.
5.5 Serial Wire Viewer (SWV)
The CPU uses the TPIU macro inside the processor to support the serial wire viewer (SWV) interface (a
single line interface).
The following sequence is needed to enable SWV output on the CPU.
1. Enable trace system by setting [CPU_SCS:DEMCR.TRCENA].
2. Unlock ITM configuration by writing to the Lock Access Register [CPU_ITM:LAR].
3. Enable ITM by setting [CPU_ITM:TCR.ITMENA].
4. Enable the desired stimulus port (0-31) in [CPU_ITM:TER].
5. Change formatter configuration if needed [CPU_TPIU:FFCR].
6. Change the pin protocol if needed [CPU_TPIU:SPPR].
7. Set the baudrate in [CPU_TPIU:ACPR].
8. The SWV can be mapped to DIO n by writing the corresponding port ID in the [IOC:IOCFGn] register.
Writes to [CPU_ITM:STIMn] registers (assuming that they are enabled) will trigger a transmit on SWV
output if the FIFO is not full.
5.6 Halt In Boot (HIB)
CC26xx devices implement a mechanism to ensure that the external emulator can take control of the
device before it executes any application code. This mechanism is called halt in boot (HIB). When HIB
detects debug activity , the boot code stops in a wait for interrupt instruction (WFI) at the end of its
execution before jumping to the application code in Flash.
Detection of activities on the TCK pin (which powers-up the JTAG power domain) is the condition for HIB
when next boot occurs. If JTAG power domain is turned off by entering the test logic reset (TLR) state
before a system reset occurs, the HIB conditions can be cleared. The HIB conditions will not be cleared if
AON_WUC:SHUTDOWN.EN is written to 1.
To exit HIB, the external emulator must connect to the device and first HALT, then RESUME the CPU
through DAP. After resuming, the program execution continues from the application code.
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JTAG Interface SWCU117A–February 2015–Revised March 2015
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