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ICEPick™

Table 5-21. Secondary Debug TAP Register [SDTR] (continued)

Bit Field Width Type Reset Description

When 0, there is not a TAP assigned to this spot.

When 1, this TAP exists in the device.

0 TapPresent 1 R -

If a TAP does not exist, the rest of the controls and status

bits in this register are considered to be non-operational.

407

SWCU117A–February 2015–Revised March 2015 JTAG Interface

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