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5.3.4.2 Test TAP Linking Block
The Test TAP Linking block contains the control and status registers shown in Table 5-18 . These
registers are used in to select of secondary TAPs into the master scan path. Each TAP has its own Test
TAP Control and Status register.
Table 5-18. Test TAP Linking Registers
Register Register Name
0x0 Secondary Test TAP 0 Register
0x1 Secondary Test TAP 1 Register
0x2 Secondary Test TAP 2 Register
0x3 Secondary Test TAP 3 Register
0x4 Secondary Test TAP 4 Register
0x5 Secondary Test TAP 5 Register
0x6-0xF Reserved
5.3.4.2.1 Secondary Test TAP Register
Table 5-19. Secondary Test TAP Register [STTR]
Bit Field Width Type Reset Description
23-10 Reserved 14 RW 0 Reserved
9 VisibleTAP 1 R – SeeTable 5-21
8 SelectTAP 1 RW 0 SeeTable 5-21
7-2 Reserved 6 R 0
1 TapAccessible 1 R – SeeTable 5-21
0 TapPresent 1 R – SeeTable 5-21
5.3.4.3 Debug TAP Linking Block
The Debug TAP Linking block contains the control and status registers used in the selection of secondary
TAPs into the master scan path. The secondary debug tap has its own Debug TAP Control and Status
register. Refer to Table 5-20 for more details.
Table 5-20. Debug TAP Linking Registers
Register Register Name
0x0 Secondary Debug TAP 0 Register
0x1-0xF Reserved
5.3.4.3.1 Secondary Debug TAP Register
Table 5-21 shows the secondary debug TAP register [SDTR].
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SWCU117A–February 2015–Revised March 2015 JTAG Interface
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