User manual

Coretex-M3 Core Registers

www.ti.com

2.5.2.16 Program Counter (PC)

Table 2-18. Program Counter (PC)

Address Offset Reset –

Physical Address Instance

Description

The Program Counter (PC) is register R15, and it contains the current program address. On reset, the processor loads the PC with the

value of the reset vector, which is at address 0x0000 0004. Bit 0 of the reset vector is loaded into the THUMB bit of the EPSR register at

reset and must be 1. The PC register can be accessed in either privileged or unprivileged mode

Type R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bits Field Name Description Type Reset

31:0 PC This field is the current program address. RW —

2.5.2.17 Program Status Register (PSR)

Table 2-19. PSR Register Combinations

PSR R/W

(1) (2)

APSR, EPSR, and IPSR

IEPSR RO EPSR and IPSR

IAPSR R/W APSR and IPSR

EAPSR R/W APSR and EPSR

(1)

Reads of the EPSR bits directly using the MSR instruction return 0, and the processor ignores writes to these bits.

(2)

The processor ignores writes to the IPSR bits.

SWCU117A–February 2015–Revised March 2015

Submit Documentation Feedback