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Table 5-5. Slave TAP Order
No Test TAP Name Description Availability for End User
Test Banks
0 TEST DFT functionalities and profiler See
(1)
1 PBIST1.0 RAM BIST controller interface Locked
2 PBIST2.0 ROM BIST controller interface Locked
3 eFuse eFuse interface for SRAM repair Locked
PD override control/status in
4 PRCM Locked
MCU VD
5 AON WUC VD override control/status See
(2)
Debug Banks
0 CM3 DAP for CM3 debug See
(2)(3)
(1)
The test TAP is locked for all devices except CC2650. This TAP implements a profiler register which can be used to extract runtime
information about program execution and general chip status. The access to this TAP can be blocked by writing to corresponding field in
customer configuration area
(2)
Some of the registers in AON WUC TAP are open for end user. This includes registers for requesting chip erase, system reset, and MCU
reset.
(3)
The access to debug port of the CPU can be blocked by writing to corresponding field in customer configuration area.
5.3.1.1 Slave DAP (CPU DAP)
The debug subsystem has only one slave DAP (CPU DAP). This debug port implements Serial Wire JTAG
Debug Port (SWJ-DP) interface which allows external access to an Advanced High-performance Bus
Access Port (AHB-AP) interface for debug accesses in the CPU.
The SWJ-DP is a standard CoreSight™ debug port that combines JTAG-DP and Serial Wire Debug Port
(SW-DP). Even though the SW-DP interface is supported by SWJ-DP, the CC26xx family does not use
this mode. The key reason is that SW-DP becomes redundant for the design in the presence of the 2-pin
JTAG (1149.7) mode.
5.3.1.2 Ordering Slave TAPs and DAPs
• When a single secondary TAP is selected, it is effectively connected to the TDO of the ICEPick TAP.
• When one or more secondary TAPs are selected, they are linked from the lowest-numbered TAP to
the highest-numbered TAP.
• The lowest-numbered TAP selected is connected closest to the device-level TDI (except for ICEPick),
while the highest-numbered TAP is connected closest to the device TDO.
• Any selected TAPs within the test bank are linked before any TAPs within the debug bank (DAP for
example).
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JTAG Interface SWCU117A–February 2015–Revised March 2015
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