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Coretex-M3 Core Registers

2.5.2.14 Stack Pointer (SP)

Table 2-16. Stack Pointer (SP)

Address Offset Reset –

Physical Address Instance

Description

The Stack Pointer (SP) is register R13. In thread mode, the function of this register changes depending on the ASP bit in the Control

Register (CONTROL) register. When the ASP bit is clear, this register is the Main Stack Pointer (MSP). When the ASP bit is set, this

register is the Process Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value from address

0x0000 0000. The MSP can only be accessed in privileged mode; the PSP can be accessed in either privileged or unprivileged mode.

Type R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bits Field Name Description Type Reset

31:0 SP This field is the address of the stack pointer. RW —

2.5.2.15 Link Register (LR)

Table 2-17. Link Register (LR)

Address Offset Reset 0xFFFF FFFF

Physical Address Instance

Description

The Link Register (LR) is register R14, and it stores the return information for subroutines, function calls, and exceptions. LR can be

accessed from either privileged or unprivileged mode.

EXC_RETURN is loaded into LR on exception entry. See Table 4-4, Exception Return Behavior, for the values and description.

Type R/W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LINK

Bits Field Name Description Type Reset

31:0 LINK This field is the return address. RW 0xFFFF FFFF

SWCU117A–February 2015–Revised March 2015

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