User manual

Chapter 5

SWCU117A–February 2015–Revised March 2015

JTAG Interface

This chapter describes the cJTAG and JTAG interface for on-chip debug support.

Table 5-1. References

ID Description

IEEE Standard Test Access Port and Boundary Scan Architecture, IEEE Std 1149.1a

[1] 1993 and Supplement Std. 1149.1b 1994, The Institute of Electrical and Electronics

Engineers, Inc.

IEEE 1149.7 Standard for Reduced-Pin and Enhanced-Functionality Test Access Port

[2]

and Boundary-Scan Architecture

Topic ........................................................................................................................... Page

5.1 Top Level Debug System................................................................................... 390

5.2 cJTAG............................................................................................................. 392

5.3 ICEPick™ ........................................................................................................ 397

5.4 ICEMelter™...................................................................................................... 408

5.5 Serial Wire Viewer (SWV)................................................................................... 408

5.6 Halt In Boot (HIB).............................................................................................. 408

5.7 Debug and Shutdown........................................................................................ 409

5.8 Debug Features Supported Through WUC TAP.................................................... 409

5.9 Profiler Register ............................................................................................... 409

389

SWCU117A–February 2015–Revised March 2015 JTAG Interface

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