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Interrupts and Events Registers

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4.6.2.92 AUXSEL0 Register (Offset = 700h) [reset = X]

AUXSEL0 is shown in Figure 4-101 and described in Table 4-107.

Output Selection for AUX Subscriber 0

Figure 4-101. AUXSEL0 Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED EV

R-X R/W-10h

Table 4-107. AUXSEL0 Register Field Descriptions

Bit Field Type Reset Description

31-7 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

6-0 EV R/W 10h

Read/write selection value

0h = Always inactive

Ch = GPT2A interrupt event, controlled by GPT2:TAMR

Dh = GPT2B interrupt event, controlled by GPT2:TBMR

Eh = GPT3A interrupt event, controlled by GPT3:TAMR

Fh = GPT3B interrupt event, controlled by GPT3:TBMR

10h = GPT0A interrupt event, controlled by GPT0:TAMR

11h = GPT0B interrupt event, controlled by GPT0:TBMR

12h = GPT1A interrupt event, controlled by GPT1:TAMR

13h = GPT1B interrupt event, controlled by GPT1:TBMR

79h = Always asserted

384

Interrupts and Events SWCU117A–February 2015–Revised March 2015

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