User manual

Interrupts and Events Registers

www.ti.com

4.6.2.80 UDMACH17SSEL Register (Offset = 588h) [reset = X]

UDMACH17SSEL is shown in Figure 4-89 and described in Table 4-95.

Output Selection for DMA Channel 17 SREQ

Figure 4-89. UDMACH17SSEL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED EV

R-X R-2Fh

Table 4-95. UDMACH17SSEL Register Field Descriptions

Bit Field Type Reset Description

31-7 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

6-0 EV R 2Fh

Read only selection value

2Fh = SSI1 TX DMA single request, controlled by

SSI0:DMACR.TXDMAE

368

Interrupts and Events SWCU117A–February 2015–Revised March 2015

Submit Documentation Feedback