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Interrupts and Events Registers

4.6.2.77 UDMACH15BSEL Register (Offset = 57Ch) [reset = X]

UDMACH15BSEL is shown in Figure 4-86 and described in Table 4-92.

Output Selection for DMA Channel 15 REQ

Figure 4-86. UDMACH15BSEL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED EV

R-X R-7h

Table 4-92. UDMACH15BSEL Register Field Descriptions

Bit Field Type Reset Description

31-7 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

6-0 EV R 7h

Read only selection value

7h = Event from AON_RTC controlled by the

AON_RTC:CTL.COMB_EV_MASK setting

365

SWCU117A–February 2015–Revised March 2015 Interrupts and Events

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