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Interrupts and Events Registers

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Table 4-91. UDMACH14BSEL Register Field Descriptions (continued)

Bit Field Type Reset Description

27h = Combined DMA done corresponding flags are here

UDMA0:REQDONE

28h = SSI0 RX DMA burst request , controlled by

SSI0:DMACR.RXDMAE

29h = SSI0 RX DMA single request, controlled by

SSI0:DMACR.RXDMAE

2Ah = SSI0 TX DMA burst request , controlled by

SSI0:DMACR.TXDMAE

2Bh = SSI0 TX DMA single request, controlled by

SSI0:DMACR.TXDMAE

2Ch = SSI1 RX DMA burst request , controlled by

SSI0:DMACR.RXDMAE

2Dh = SSI1 RX DMA single request, controlled by

SSI0:DMACR.RXDMAE

2Eh = SSI1 TX DMA burst request , controlled by

SSI0:DMACR.TXDMAE

2Fh = SSI1 TX DMA single request, controlled by

SSI0:DMACR.TXDMAE

30h = UART0 RX DMA burst request, controlled by

UART0:DMACTL.RXDMAE

31h = UART0 RX DMA single request, controlled by

UART0:DMACTL.RXDMAE

32h = UART0 TX DMA burst request, controlled by

UART0:DMACTL.TXDMAE

33h = UART0 TX DMA single request, controlled by

UART0:DMACTL.TXDMAE

38h = SPIS Combined event, the flags are found here

SPIS:GPFLAGS

39h = SPIS RX FIFO DMA burst request, controlled by

SPIS:CFG.TR_DMA_REQ_TYPE

3Ah = SPIS RX FIFO DMA single request, controlled by

SPIS:CFG.TR_DMA_REQ_TYPE

3Bh = SPIS TX FIFO DMA burst request, controlled by

SPIS:CFG.TX_DMA_REQ_TYPE

3Ch = SPIS TX FIFO DMA single request, controlled by

SPIS:CFG.TX_DMA_REQ_TYPE

3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT

3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT

3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT

40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT

41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT

42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT

43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT

44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT

4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV

4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV

4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV

50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV

51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV

52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV

53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV

54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV

55h = Port capture event from IOC, configured by

IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM

PORT_EVENT0 wil be routed here.

56h = Port capture event from IOC, configured by

IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM

PORT_EVENT1 wil be routed here.

57h = Port capture event from IOC, configured by

IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM

PORT_EVENT2 wil be routed here.

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Interrupts and Events SWCU117A–February 2015–Revised March 2015

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