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Interrupts and Events Registers

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4.6.2.62 UDMACH6BSEL Register (Offset = 534h) [reset = X]

UDMACH6BSEL is shown in Figure 4-71 and described in Table 4-77.

Output Selection for DMA Channel 6 REQ

Figure 4-71. UDMACH6BSEL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED EV

R-X R-3Bh

Table 4-77. UDMACH6BSEL Register Field Descriptions

Bit Field Type Reset Description

31-7 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

6-0 EV R 3Bh

Read only selection value

3Bh = SPIS TX FIFO DMA burst request, controlled by

SPIS:CFG.TX_DMA_REQ_TYPE

346

Interrupts and Events SWCU117A–February 2015–Revised March 2015

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