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Interrupts and Events Registers

4.6.2.61 UDMACH6SSEL Register (Offset = 530h) [reset = X]

UDMACH6SSEL is shown in Figure 4-70 and described in Table 4-76.

Output Selection for DMA Channel 6 SREQ

Figure 4-70. UDMACH6SSEL Register

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESERVED EV

R-X R-3Ch

Table 4-76. UDMACH6SSEL Register Field Descriptions

Bit Field Type Reset Description

31-7 RESERVED R X

Software should not rely on the value of a reserved. Writing any

other value than the reset value may result in undefined behavior.

6-0 EV R 3Ch

Read only selection value

3Ch = SPIS TX FIFO DMA single request, controlled by

SPIS:CFG.TX_DMA_REQ_TYPE

345

SWCU117A–February 2015–Revised March 2015 Interrupts and Events

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